A phase-change memory or phase-change random access memory (PRAM) as referred to herein is also referred to as an ovonic unified memory (OUM) in the art. The OUM cell is based on a volume of chalcogenide alloy, which, after being heated and cooled, adopts one of two stable, but programmable, phases: crystalline or amorphous. The resistance of the first phase, i.e., the crystalline phase, is relatively low, and the resistance of the second phase, i.e., the amorphous phase, is relatively high. A programming of the state of the cell to a logical one (1) or zero (0) depends on the phase of the programmable volume, and is determined by measuring its resistance. The crystalline, or conductive, state is commonly referred to as the “set”, or “0”, state; and the amorphous or resistive non-conductive state is commonly referred to as the “reset”, or “1”, state.
To make the programmable volume amorphous, it is heated above its melting point by a resistive heater. To make the programmable volume crystalline, it is heated to just below its melting point for a short period of time, e.g., 50 ns, so that the atoms line up in their crystalline locations. The volume cools rapidly into the stable amorphous or stable crystalline states when the heater is turned off. In this manner, data is written to the cell by programming the cell to either the crystalline or amorphous states. Reading of the programmed cell is performed by a sense amplifier measuring the resistance of the programmed cell.
The key to the phase-change memory is the chalcogenide material. The device historically includes an alloy of germanium (Ge), antimony (Sb) and tellurium (Te), which is referred to commonly as a GST alloy. The material is particularly useful for incorporation in a memory device because of its ability to switch rapidly, when heated and cooled, between the stable amorphous and crystalline phases.
A memory cell that incorporates a chalcogenide material typically includes a top electrode, a patterned layer, or volume, of the chalcogenide material, and a lower electrode that serves as a resistive heating element. FIG. 1 is a schematic diagram illustrating a memory cell 10 which uses the programmable chalcogenide material. The cell 10 includes a conductive top electrode 12 formed over the programmable phase change chalcogenide material 14. A conductive bottom electrode contact (BEC) 16 is formed under the programmable material 14. The bottom electrode contact (BEC) is formed of a higher resistivity material such as TiAlN, TiN, and the like, so that is operates as a resistive heater by generating heat when current flows through the BEC. An access transistor 20 (see FIGS. 2A and 2B) is connected to the bottom electrode contact 16 for controlling the flow of current through the cell 10. The gate of the access transistor 20 is commonly connected to a word line WL of the memory device incorporating the cell 10.
FIGS. 2A and 2B are schematic diagrams which illustrate the cell 10 in each of the two programmed states. In FIG. 2A, the cell 10 is shown in the conductive set, or “0”, state. In this state, some portion of the programmable material 14 in contact with the BEC is in the crystalline state. In FIG. 2B, the cell 10 is shown in the resistive reset, or “1”, state. In this state, some portion of the programmable material 14 in contact with the BEC is in the amorphous state.
FIG. 3 is a schematic diagram schematically illustrating the electrical configuration of the cell 10. A word line WL controls the flow of current through the cell 10 at the gate of access transistor 20. The resulting current flowing through the cell 10, ICELL, and activation of the bit line BL connected to the top electrode 12 of the cell 10 serves to program the state of the cell 10 during a writing, or programming operation, and serves as a parameter for reading the state of the cell 10 during a reading, or sensing, operation.
FIG. 4 is a timing diagram illustrating programming of a memory cell that includes a volume of programmable chalcogenide material, for example of the type illustrated and described above in connection with FIGS. 1-3. The timing diagram of FIG. 4 is a graph of temperature with respect to time illustrating the programming pulses of heat used in conventional apparatus for programming the material to the set (crystalline) state and the reset (amorphous) state. The curve labeled 22 illustrates the time-temperature relationship for the reset pulse, i.e., the temperature pulse used to program the material to the reset (amorphous) state; and the curve labeled 24 illustrates the time-temperature relationship for the set pulse, i.e., the temperature pulse used to program the material to the set (crystalline) state.
Referring to the curve labeled 22 in FIG. 4, to change the programmable volume of chalcogenide material to the amorphous phase (reset state), the chalcogenide alloy is heated to a temperature above its melting point (Tm), by a resistive heater. The heating pulse is applied for a relatively short period of time, e.g., a few nanoseconds. The alloy cools rapidly when the heater is turned off over a time period T1, referred to as a quenching period, to a temperature that is below the crystallization temperature Tc of the volume. Following the quenching period, the volume of chalcogenide material is placed in a stable, amorphous state.
Referring to the curve labeled 24 in FIG. 4, to change the programmable volume to the crystalline phase (set state), the alloy is heated to a temperature below its melting point Tm, for example, to a temperate between the crystallization temperature Tc and the melting temperature Tm of the material, by the resistive heater. The temperature is maintained for a time period T2 that is relatively longer than the time period T1 to allow portions of the alloy to crystallize, that is, to allow the atoms in the material to align in their crystalline structure. The alloy cools rapidly when the heater is turned off, to a temperature that is below the crystallization temperature Tc of the volume. After the crystallization is achieved, the set heating pulse is removed, and the material cools to a stable, crystalline state.
Research has been conducted toward the fabrication of PRAM devices that have multiple programmable states. For example, while the above examples demonstrate PRAM cells having two states, namely amorphous (reset) and crystalline (set), others have experimented with PRAM cells having multiple so-called “hybrid”, or “intermediate”, states between the amorphous and crystalline “end” states. In the intermediate states, the programmable volume is partially amorphous and partially crystalline, and by controlling the relative percentages of amorphous and crystalline volumes of programmable material, the resulting resistance of the cell can be controlled. In this manner, each resulting PRAM cell can be said to have multiple programmable states, or multiple levels, each corresponding to a unique resistance value. Research in the field of multiple-level PRAMs has been conducted by Itri, et al., “Analysis of phase-transformation dynamics and estimation of amorphous-chalcogenide fraction in phase-change memories,” IEEE 42nd Annual International Reliability Physics Symposium, Phoenix, 2004, pp 209-215, the content of which is incorporated herein by reference.
Others have determined that the resistance value of a programmed chalcogenide volume can vary with time. See, for example, Pirovano, et al., “Low-Field Amorphous State Resistance and Threshold Voltage Drift in Chalcogenide Materials,” IEEE Transactions on Electron Devices, Vol. 51, No. 5, May 2004, pp 714-719, the content of which is incorporated herein by reference. The resulting “resistance drift” is especially significant in the amorphous state of a two-level PRAM cell, and in the partially amorphous intermediate states and the fully amorphous state of the multiple-level PRAM cell.
In an attempt to control resistance drift, others have studied the behavior of resistance drift dynamics. See, for example, Ielmini, et al., “Recovery and Drift Dynamics of Resistance and Threshold Voltages in Phase-Change Memories,” IEEE Transactions on Electron Devices, Vol. 54, No. 2, February 2007, pp 308-315, the content of which is incorporated herein by reference. However, resistance drift remains a difficult problem to address, especially in multiple-level PRAM devices.